Renesas unveils new DDR5 memory chips
On DDR5, Renesas has announced two new DDR5 DIMM chips for improving server and client performance in emerging applications. At present, under the constraints of the von Neumann architecture, DDR4 seems to have reached its limit. In order to solve the memory wall problem, the memory needs to be upgraded as soon as possible.
Renesas' announcement includes two new products: a third-generation register clock driver (RCD) and a new client clock driver (CKD). Each chip plays a vital (albeit very different) role in a high-performance computing system. This article summarizes the metrics for these chips and provides insight into how they affect server-side and client-side computing.
Server side clock driver
While it may not directly improve a DIMM's performance under typical conditions, RCD allows server-grade memory to maintain its maximum 6400MT/s performance under all temperature and load conditions, improving reliability and computing speed in non-ideal situations. Additionally, integration with other DIMM peripherals, such as SPD hubs, temperature sensors, and power management ICs, opens up a host of new options for server memory designers.
The 3rd generation RCD can support transmission speed up to 6400MT/s, Rambus also added SPD and temperature IC to its product portfolio shortly after releasing the 3rd generation RCD. A key difference between the two chips is the support for LRDIMMs in the Renesas design. However, it's too early to fully compare the performance of the two.
DDR5 Client Side Memory
While the RCD addresses the speed of server-side memory, Renesas is also aiming to improve client-side DDR5 DIMMs with its first-generation CKD.Similar to the RCD, the CKD is designed to provide a buffer between the input and output clocks, providing more stability for high-speed and next-generation applications.
CKD supports input clock rates up to 3600 MHz and a maximum transfer speed of 7200 MT/s. Designers can take advantage of three operating modes in which one, both, or both of the two input clocks are disabled to the PLL to drive the corresponding output pair. The I2C and I3C buses also provide access to internal control registers for device configuration.
RCD and CKD are available in FCBGA and FCCSP packages and are expected to be available in volume in the first half of 2024. In addition, Renesas has combined the new chip with other chips as part of its "winning portfolio," speeding up time-to-market for designs using Renesas parts.
DDR5 for everyone
While these advances from Renesas may only directly benefit the engineers designing DIMMs, they could ultimately affect everyone who touches the HPC market, both designers and users. Improved transfer speeds, combined with higher processing power, will ultimately lead to better computing performance for memory-intensive applications.
Judging from the innovations of Renesas and Rambus, DDR5 seems to be becoming a better choice for high-performance client-side and server-side applications, resulting in higher performance and efficiency, which can save power. With its high performance, DDR5 is bound to gain popularity rapidly.
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