Highly Integrated Clock ICs for Wireless Infrastructure Applications
Silicon Labs' Si5380 clock generator is a single-chip device that can replace low phase noise integer-N clocks, voltage-controlled crystal oscillators (VCXOs), discrete loop filters, and voltage regulators. The Si5380 clock ICs offer phase noise performance comparable to traditional discrete solutions while offering significant advantages in package size, bill of material (BOM), power consumption, performance and ease of use.
The Si5380 clock IC provides a targeted and optimized solution for the design of the remote radio head (RRH) of the next generation of microcell and macrocell base stations with the latest fourth-generation DSPLL technology from Silicon Labs. DSPLL technology's innovative dual-loop mixed-signal architecture integrates a high-performance 15GHz analog voltage-controlled oscillator in a digital phase-locked loop (PLL) architecture, eliminating the typically required discrete loop filter and low-dropout output (LDO) Stabilizer. This enables this clocking solution to provide the best combination of ultra-low phase noise clock synthesis and best-in-class PLL integration.
Compared with competing VCXO clock IC solutions, the Si5380 clock IC can reduce printed circuit board (PCB) area by 66% and reduce power consumption by 30%. Today's femtocells typically have constrained power budgets and are typically powered using Power over Ethernet (PoE), so energy-efficient timing devices are especially important. With the integration of all PLL and power regulation circuits in the DSPLL, the Si5380 chip can provide extremely high board-level noise rejection, power supply noise rejection and consistent, repeatable phase noise performance over the operating temperature range.
VCXO-based clock solutions usually lead to spurious performance degradation in vibration environments, while the integrated DSPLL technology of the Si5380 chip can provide excellent spurious response in any system environment. In addition, the Si5380 clock chip can guarantee low phase noise after locking to the high-jitter input clock, ensuring that the performance of the data converter will not be degraded by external influences. The Si5380 is capable of generating 4G/LTE frequencies up to 1.47456GHz and provides 12 independently configurable clock outputs to provide timing services for JESD204B compliant data converters, FPGAs and other logic devices.
James Wilson, Timing Product Marketing Director of Silicon Labs, said: "The Si5380 clock is currently the most integrated timing solution in the industry. It meets the requirements of compact PCB packaging, low power consumption, reliability and Carrier-level phase noise performance requirements. Silicon Labs' highly integrated DSPLL clock architecture, combined with the easy-to-use ClockBuilder Pro software, greatly simplifies the design difficulty of clock synthesis and jitter attenuation required by today's heterogeneous wireless networks."
Simplify Clock Tree Design with ClockBuilder Pro
To simplify clock tree design for wireless base stations, Silicon Labs' ClockBuilder Pro software enables designers to generate programmable Si5380 clock configurations in less than five minutes, minimizing software development costs. Instead of waiting months for a custom clock chip, designers simply upload their custom configuration to Silicon Labs through ClockBuilder Pro, and factory pre-programmed Si5380 clock samples can be shipped within two weeks. With the industry's shortest lead times for custom samples, customers can significantly accelerate the entire product development process.
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