what are the differences between AI chips and traditional chips?
What is an AI chip？
AI chips are specifically designed to accelerate artificial intelligence tasks such as machine learning and deep learning. They employ specific hardware architectures such as Graphics Processing Units (GPUs), Tensor Processing Units (TPUs), and Neural Network Processing Units (NPUs) to enable efficient parallel computing and optimized algorithmic operations. Whereas traditional chips are universally designed to perform a variety of common tasks like computation, storage and communication.
Origin of AI chips
In the 1970s, Ted Hoff, a scientist at AT&T Bell Labs, proposed the concept of the "microprocessor" and in 1971 introduced the world's first microprocessor, the Intel 4004. This microprocessor not only made the computer manufacturing cost significantly reduced, but also laid the foundation for the development of artificial intelligence chips in the future. In the five years after this, people found that GPU parallel computing ability, just to adapt to the needs of AI algorithms and data parallel computing, began to gradually try to use GPU to run AI algorithms and verification.
So what are the differences between AI chips and traditional chips?
The most common application scenarios of AI chips are: data center, automatic driving, etc. requires great computing power to compare with the data center scenario, the computing needs of automatic driving will be very different - automatic driving is to deal with the flow of data, sensory data constantly through a variety of sensors to arrive at the car, the chip must be immediately processed data, and the lower the latency, the better. The chip must process the data immediately, and the lower the latency, the better. The lower the latency, the better it will be able to react to the surrounding situation, brake in time and control the amount of traffic to ensure safety. Autonomous driving and data center scenarios are different, resulting in different chip architecture design trade-offs.
The following lists several application aspects of AI chips in self-driving cars:
(1) Sensor data processing:
Sensing processing is a typical application scenario of AI in autonomous driving. Self-driving cars need to obtain road and environment information through a variety of sensors, such as LIDAR, cameras, ultrasonic sensors, etc. AI chips combine these data through efficient data processing and analysis, thus trying to realize accurate perception of the road and environment.
(2) Decision-making and control:
Decision planning processing is another important application scenario of AI in autonomous driving, autonomous driving cars need to carry out several tasks at the same time, such as planning routes, identifying obstacles and traffic signals, etc. By processing these signals quickly and reacting instantly, AI chips can dispatch the control system of the car in the shortest possible time, thus ensuring the safety of the car and accurate driving. Traditional control methods include PID control, sliding mode control, fuzzy control, model predictive control, etc.
(3) Self-learning and upgrading:
AI chips can optimize and upgrade the algorithms that realize autonomous driving technology by analyzing and learning from what happens inside and outside the car.
What is obvious from the above is that AI chips are chips designed to optimize specific algorithms, just as we are now very common use of picture recognition, real-time translation, text recognition and other applications, behind them all need the participation of deep learning, and AI chips provide arithmetic support for deep learning. With more and more demands, we need stronger chips to get the job done faster and better, and CPUs are no longer enough to support these unique needs.
In addition to the arithmetic module, the CPU contains many external units. To ensure compatibility, the CPU architecture is limited in its computing power. In particular, machine learning algorithms involve a large number of matrix and floating-point operations. For logic judgment and addressing aspects are kept as concise as possible. Therefore, it is possible to economize on logic operations, addressing, coding, and hosting within the permitted range, and incorporate more floating-point operation units. The familiar GPU and FPGA can be called a part of the large family of AI chips. GPUs are simplified on the basis of the CPU, adding more floating-point units, so GPUs are more suitable for a large number of arithmetic calculations and fewer occasions of logical operations, such as image convolution, Fourier transform.
Power consumption and price, AI chips will have greater power consumption and more expensive, GPU is one of the obvious examples.
There are two broad design approaches used for AI chips:
AI chips are large-scale digital integrated circuits, and most companies still opt for an automated synthesis + layout and wiring design flow based on IP and standard digital cells, with some stronger digital design departments (especially IP providers) doing semi-customized designs on key data paths. Another design approach is more often found in labs and prototypes of startups, such as Flash process-based memory-computer integration design, analog circuit-based arrays of computing units, etc. These require a deep foundation in process-related circuit design, and their products have room for application in some fields (e.g., extremely low-power smart headphones). This is also a unique realization after the emergence of AI chips, which can be said to be quite different from traditional chips.
To summarize, AI chips focus on accelerating artificial intelligence tasks with highly parallel computing and low power consumption, while traditional chips are suitable for a variety of general-purpose computing and data processing tasks.
In the future, AI chips will face growing artificial intelligence market demand and technical challenges, while traditional chips need to adapt to emerging application areas and ever-increasing performance requirements, and now the hardware computing power is greater than the performance of data reading and accessing, and when the computational unit is not the bottleneck, how to reduce the memory access latency will perhaps become the next research direction.
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